Setup & Hold, made visible.
Drive a launch flip-flop into a capture flip-flop, dial in clock skew, jitter, cell strength, and Vt choice, and watch the setup and hold inequalities resolve in real time — waveforms, numbers, and margin, all in one place.
STA always checks a launch point against a capture point. Pick which segment you're analyzing — the reference diagram, the waveform, and the slack equations below all switch together.
Full-cycle: the capture flip-flop is clocked by the same (non-inverted) edge as the launch flip-flop, one period later. This is the ordinary REG→REG, IN→REG, REG→OUT case.
Reference path
Launch / capture waveform
Showing the setup and hold checks for the IN → REG path — live substitution of every value on the bench into the two governing inequalities.
Setup check
METHold check
METTcq — clock-to-Q
nominal × Vt factor, then ±6% OCV
Tcomb — base logic
baseDelay × sizing × Vt, then ±6% OCV
Buffer / delay cells
scales with sizing & Vt like any other cell, then ±4% OCV (tighter — simpler, well-characterized cells)
Tskew — clock skew
realized as clock buffers, ±4% OCV on their total delay
Positive skew
Delays the capture edge relative to launch. It widens the setup window (more time to arrive) but shrinks the hold window (data can be overwritten if it arrives too fast) — you're borrowing margin from hold to pay setup.
Negative skew
Delays the launch edge relative to capture instead. This tightens setup (less time to arrive before the next capture edge) but relaxes hold — the opposite trade.
Cell upsizing
A stronger gate drives its output capacitance faster, cutting T_comb. Great for setup (less delay to beat the clock) but can worsen hold if the path becomes fast enough to arrive before the hold window closes.
Cell downsizing
A weaker gate is slower but smaller and lower-power. It increases T_comb, which can help a hold violation "for free" — sometimes intentionally used as a low-cost fix.
LVT (low Vt)
Lower threshold voltage means more gate overdrive and faster switching — shrinks T_comb at the cost of higher leakage power. Used sparingly, on the critical (setup-limited) paths only.
HVT (high Vt)
Higher threshold voltage trades speed for leakage. Slower switching increases T_comb — useful on non-critical paths to save power, or deliberately to fix a hold violation.
Buffer / delay insertion
Adding buffer cells purely increases T_comb without changing logic function. This is the classic, surgical fix for a hold violation, since hold has no clock-period dependence to exploit.
Jitter
Cycle-to-cycle clock uncertainty. It only ever works against you: subtracted from the setup budget as a guaranteed worst-case erosion of the available window.
Why hold has no Tclk
Hold is checked against the same edge that launched the data (the next edge, one period later, is irrelevant) — so the clock period cancels out of the inequality entirely. That's why raising frequency never fixes a hold violation.
Clock cells vs. data-path cells
Both are buffers, but they're built for opposite goals. Clock buffers (triangles in the diagram) are characterized for low skew, tight delay variation, and balanced rise/fall times — priorities that keep the clock edge arriving at (almost) the same instant everywhere on the chip, which is exactly how real skew gets engineered on silicon. Data buffers (rectangles in the T_comb cloud) are picked for higher drive strength to push a signal through capacitance quickly — optimized for speed and power, with no requirement to be skew-tight. Swapping them is a real failure mode, not just a labeling mismatch: dropping a data buffer into a clock tree reintroduces the delay variation clock buffers exist to remove and can break timing chip-wide, while dropping a clock buffer into a data path wastes area and power for a skew guarantee nothing there needs.